1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Increasingly integrated semiconductor devices have led to increasing miniaturization of semiconductor elements used in the semiconductor devices. In recent semiconductor devices, STI (shallow Trench Isolation) formed by filling an insulating film into a trench in a semiconductor layer is used as an isolation region. Miniaturized STI hinders the insulating film from being filled into the trench by means of a CVD method or the like during formation of the STI. Thus, for the formation of the STI, a method has been proposed which fills an interior of the trench with a two-layer structure including an SOD (Spin On Dielectrics) film that can be formed by applying polysilazane or the like and a silicon oxide film (SiO2) formed by the CVD method (Japanese Patent Laid-Open No. 2002-203895).
Furthermore, as a result of the miniaturization, instead of related planar transistors, a new type of transistor has been used as a MOS transistor. The new type of transistor includes a trench-shaped gate electrode that effectively prevents a possible short channel effect or a channel layer formed on a side surface portion of a trench for the gate electrode (Japanese Patent Laid-Open No. 2007-158269).
Thus, as a semiconductor device such as a DRAM which can be miniaturized and which includes, on a semiconductor chip, a memory cell region and a peripheral circuit region that is different from the memory cell region, a possible semiconductor device includes, in a memory cell region, an isolation region of the STI with a two-layer structure such as the one described in Japanese Patent Laid-Open No. 2002-203895 and a transistor including a trench-shaped gate electrode structure.
The present inventor has recognized that the semiconductor device with the transistor including the trench-shaped gate electrode structure may pose problems described below.
In the description below, a DRAM including a memory cell with an isolation region of the STI with a two-layer structure will be taken by way of an example.
FIG. 1 is a plan view schematically showing location of an isolation region in an end region of a memory cell in a related DRAM. Reference numeral 101 denotes an active region (impurity diffusion layer region) forming a memory cell. A plurality of active regions are arranged according to a predetermined rule. Each of the active regions is formed by forming isolation region 100 formed of the STI on a semiconductor substrate (not shown in the drawings) to partition the semiconductor substrate. Reference numeral 101a denotes an active region located at an end of a memory cell region.
Reference numeral 102 denotes an active region formed at a boundary portion between the memory cell region and a peripheral circuit region and used to, for example, fix a substrate potential (well potential) of the memory cell region. The isolation region positioned between terminal active region 101a and active region 102 is denoted by D1. The isolation region between active regions 101 in the memory cell region is denoted by D2. The isolation region between active region 101a at the end of the memory cell and the active region located adjacent to active region 101a is similarly denoted by D2.
A method for forming isolation region 100 will be described with reference to FIGS. 2 and 3 in sectional views taken along line A-A′ in FIG. 1.
As shown in FIG. 2, silicon nitride film (Si3N4) 105 is used to form a mask pattern on a semiconductor substrate 200 so that the mask pattern covers the active regions. Etching is then performed to form trenches 104 in semiconductor substrate 200. A silicon nitride film is formed in each of trenches 104 as liner film 106. Then, trench 104 is filled with SOD region 107 made of polysilazane or the like. Thermal treatment is then performed in a high-temperature oxidizing atmosphere to convert (reform) SOD region 107 into a dense film.
Thereafter, SOD region 107 is partly removed by wet etching so as to remain in trench 104. An exposed portion of liner film 106 is also removed. The conversion of SOD region 107 into the dense film progresses more easily in isolation region D1 positioned at the end of the memory cell than in isolation region D2 in the memory cell region.
The reason is that the opening width of the trench in isolation region D1 is larger than that in isolation region D2. Thus, during the thermal treatment, oxygen is more easily supplied to the SOD region in isolation region D1. Thus, when SOD region 107 is partly removed, an etching rate for the SOD region is higher in isolation region D2 than in isolation region D1. The amount of remaining SOD region 107 (the film thickness of SOD region 107 from a bottom portion of the trench) is larger in isolation region D1 at the end of the memory cell region, than in isolation region D2 inside the memory cell region.
Then, as shown in FIG. 3, an insulating film such as silicon oxide film 108 which is formed by the CVD method is filled on SOD region 107 in the trench. Thereafter, a surface of the insulating film is flattened by a CMP method to remove silicon nitride film 105 for the mask. Moreover, silicon oxide film 108 is partly removed by wet etching. A surface of remaining silicon oxide film 108 is flattened to complete an isolation region.
Then, a trench-shaped gate electrode of a MOS transistor functioning as a word line is formed in the memory cell region. FIG. 4 is a plan view showing location of trenches 110 for gate electrodes. Each of trenches 110 is located so as to completely cross all active regions 101, including the terminal active region 101a. 
FIG. 5 shows a cross section of the semiconductor device in which a trench pattern has been formed, the cross section being taken along line A-A′. FIGS. 6 and 7 show cross sections taken along line B-B′. In FIG. 5, reference numeral 115 denotes a silicon nitride film used as a mask when trench 110 is formed by etching. An opening is formed at the position of trench 110. In FIG. 6, trench 110 is formed in a portion of the substrate which is not covered with silicon nitride film 115 for the mask. During the formation of the trench, semiconductor substrate 200 is etched, and the insulating film in the isolation region is etched away. However, the semiconductor substrate is etched deeper owing to an etching selection ratio.
In isolation region D1 at the end of the memory cell region, silicon oxide film 108 is thin before the start of the etching. Thus, during the formation of the trench, the etching progresses until the underlying SOD region 107 is exposed, with liner film 106 accordingly exposed. On the other hand, in isolation region D2 in the memory cell region, silicon oxide film 108 is thick. Thus, SOD region 107 and liner film 106 are prevented from being exposed.
Then, as shown in FIG. 7, silicon nitride film 115 for the mask is removed by wet etching. At this time, in isolation region D1 at the end of the memory cell region, the silicon nitride film used as liner film 106 is exposed. Thus, liner film 106 is removed to form recess portion 120. Etching of liner film 106 also progresses in a lateral direction along a boundary portion between the isolation region and the active region. Thus, recess portion 120 is formed between adjacent trenches 110.
The present inventor has recognized that in this condition, when a gate insulating film is formed and a conductive film such as polycrystalline silicon is then filled into trench 110 for the gate electrode, the conductive film may remain along recess portion 120, formed by removing liner film 106; the remaining conductive film is difficult to remove. When the conductive film thus remains along recess portion 120, a short circuit may occur between the adjacent gate electrodes. FIG. 18 is a top view showing this condition. In FIG. 18, the conductive film remaining in the recess portion is denoted by reference numerals 121 and 122. As shown in FIG. 18, conductive film 122 is present between two trenches 110. During a subsequent step, a conductive material is deposited in trench 110 to form the gate electrode. Thus, the gate electrodes formed in two trenches 110 are short-circuited by conductive film 122. Therefore, manufacturing yield may decrease as a result of an attempt to manufacture a semiconductor device with a memory cell region by the relevant method.